Sr. Design Verification Engineer

Location: San Diego, California
Posted On: 7/11/2017
Job Code: HVE_5052
Job Description
The candidate will work in a team with other DV (design verification) engineers, and will be involved in verifying RTL blocks. Experience in ASIC design and verification. Experience in verifying designs at system level and block level using constrained random verification.

Minimum Qualifications: 4-8 years industry experience. Bachelors in Engineering. Expert in System Verilog and OVM/UVM based verification. Strong experience in ASIC design verification flows and DV methodologies. Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers Strong and independent design debugging capability. Strong programming and scripting language capability. Expert in using verification tools like VCS, modelsim, Debussy etc Familiar with System Verilog Assertions, Code and Functional Coverage and Formal verification techniques.

Preferred Qualifications: Masters in Engineering. Highly motivated and be able to work both independently and as a member of team. Understanding of AHB, AXI and other bus protocols and system architecture is a plus.

Education: Required: Bachelors in Engineering Preferred: Masters in Engineering

For more information please contact Summit Sharma at 425-394-5052 or email at
Category:IT  code:new
Job Requirements
Expert in System Verilog
Expert in OVM/UVM
Strong programming (C/C++) and Scripting (Perl, Python, TCL etc)
Strong experience with verification tools like VCS, Modelsim, Debussy
SV Testbench, drivers, monitors, scoreboards, checkers

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