Design Engineer

 
Location: Austin, Texas
Posted On: 6/12/2017
Job Code: 5919_SOC_TX
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Category:IT code:new HBR
 
Job Description
 
Job Scope:
• Client is looking for world class, driven engineers with proven product development experience to develop a unique wireless Virtual Reality product

Job Duties:
• Candidate will be responsible for full-chip SoC Design-For-Test DFT flows
• At least 5 years of experience with latest industry-standard deep-submicron DFT flows and tools required
• Must have demonstrated success implementing full-chip scan, at-speed scan, scan compression and BIST
• Solid Verilog skills required, with SystemVerilog experience a plus
• Knowledge of synthesis, STA and place and route flows a plus
• Proficient with automating design flows using Perl, TCL, and Make.


To discuss further on this or to schedule an interview,
Please contact - Shivani Shah
973-867-7919
shivani.shah@collabera.com
Category:IT  code:new
 
 
Job Requirements
 
 
full-chip SoC design experience, DFT, Verilog
 

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Shivani Shah
 
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