Design Engineer

 
Location: Austin, Texas
Posted On: 6/12/2017
Job Code: AMD758_5674
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Category:IT code:new HBR
 
Job Description
 
JOB DUTIES:
• Candidate will be responsible for full-chip SoC Physical Design flows
• Experience with latest industry-standard deep-submicron Automated Place and Route (APR) and Physical Verification (PV) flows and tools required
• Must have demonstrated success taping out full-chip SoCs
• Solid Verilog skills expected
• Knowledge of synthesis, STA and DFT flows a plus
• Proficient with automating design flows using Perl, TCL, and Make.
Category:IT  code:new
 
 
Job Requirements
 
 
Verilog, Wireless, Perl, Tcl
 

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Recruiter
Kunal Arora
 
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