Design Engineer

 
Location: Austin, Texas
Posted On: 6/12/2017
Job Code: AMD757_5674
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Job Description
 
Tittle:Design Engineer
Duration:12 months
JOB DUTIES:
• Candidate will be responsible for full-chip SoC Design-For-Test DFT flows
• At least 5 years of experience with latest industry-standard deep-submicron DFT flows and tools required
• Must have demonstrated success implementing full-chip scan, at-speed scan, scan compression and BIST
• Solid Verilog skills required, with System Verilog experience a plus
• Knowledge of synthesis, STA and place and route flows a plus
• Proficient with automating design flows using Perl, TCL, and Make.
Category:IT  code:new
 
 
Job Requirements
 
 
Verilog, Wireless, Perl, Tcl
 

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Recruiter
Kunal Arora
 
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