Design Engineer -

 
Location: Austin, Texas
Posted On: 6/9/2017
Job Code: AM756
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Job Description
 
JOB DUTIES:
• Experience (5+ years) implementing Signal Processing verilog RTL targeted at ASICs required
• Experience with wireless communications protocols (Wifi, 4G, etc.) required
• SystemVerilog, Synthesis, STA, and FPGA experience preferred
• Experience with latest industry-standard deep-submicron flows a plus
• Synthesis, STA, and FPGA experience preferred
• Proficient in advanced digital design methodologies.
Category:IT  code:new
 
 
Job Requirements
 
 
Verilog, FPGA, Wireless, Digital Design, ASIC
 

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Contact Details
 
Recruiter
Abhishek Thaken
 
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