AMDJP00000724

 
Location: Markham, Ontario
Posted On: 6/8/2017
Job Code: Verification Enginee
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Job Description
 
Job Title: DFT Verification engineer

• Job Description:

RESPONSIBILITIES:
• The successful candidate will report to the SOC DFX Manager and will have the following responsibilities.
• Work with a team of verification engineers to verify DFT and DFD design of the state of the art SoC
• Write and review verification test-plans.
• Develop verification infrastructure, test-bench components and test-cases.
• Run RTL and Gates level VCS simulations of test-cases, review waveforms and debug failures.
• Drive performance verification on all DFT structures
• Generate and verify DFT structural patterns and functional patterns
• Participate in ATE bring-up and debug the DFT patterns on ATE and platform

REQUIREMENTS:
• BS in EE & CS. MS preferred, with 10+ years' experience.
• Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic.
• Excellent knowledge of verilog, C, C++ and a scripting language; experience with Perl and TCL is a plus
• Hands on working experience on ASIC DFT design and verification
• Strong knowledge of C++ and object oriented programming.
• Knowledge of UVM and OVM verification methodologies.
• Familiar with entire ASIC design flow
• Strong analytical/problem solving skills and pronounced attention to details.
• Must be a self starter, and able to independently drive tasks to completion.
Category:IT  code:new
 
 
Job Requirements
 
 
Verilog, C++, Perl, Tcl, ASIC
 

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Recruiter
Amitoz Bhalla
 
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