Audio Design Verification Engineer

 
Location: Markham, Ontario
Posted On: 6/7/2017
Job Code: DES_VER_6934
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Category:IT code:new HBR
 
Job Description
 
We are the world's leading developer of next-generation wireless and multimedia technology. Committed to building a world-class organization that will lead the industry in multimedia technology. Currently searching for an Audio Design Verification engineer interested in developing world-class multimedia and compute solutions. Successful candidates will work within a multi-discipline, multi-site team of architects, designers and verification engineers to help build next generation Mobile System-on-Chips (SoCs). KEY RESPONSIBILITIES Drive core verification during the pre/post silicon phase of next generation ASICs through simulation (C/RTL), simulation acceleration and emulation (FPGA). Drive test plan definition, test plan execution, verification closure in conjunction with the ASIC teams. Create/maintain a test bench, test suite, assertions, and functional coverage models. Partner with Design/Architectural teams. Drive debug activities through the development cycle (pre and post-silicon). Implement flows to automate development processes. Candidate will drive new initiatives/collaborations across multi-site and multi-functional teams.
Minimum Qualifications:Experience with Hardware Verification Languages (HVL) such as SystemVerilog (UVM), Vera, SystemC, etc.. Extensive experience with constrained random verification and assertion based verification methodologies. Experience with Low Power verification techniques. Knowledge of scripting languages such as Perl and/or Python. Good working experience with C and ARM assembly. Strong understanding of ASIC/VLSI concepts. Knowledge in one or more of the following disciplines would be beneficial: Audio (MP3, MIDI, etc.), Bus/interconnect (AHB, AXI), CPU (ARM v8/v7, Cache, MMU, security, etc.), Display (MIPI DSI, HDMI, etc.), Graphics (OpenGL ES, OpenVG, etc.), Camera (MIPI CSI, ISP, etc.), and/or Video (HEVC, H.264, H.263, VC-1, etc.). Experience using RTL simulators such as Synopsys VCS, Mentor Graphics Questa and/or Cadence Incisive. Detailed oriented with strong analytical and debugging skills. Strong communication skills (written and verbal) is a must
Preferred Qualifications:3-5 years Design Verification experience.
Education:Required: Bachelor's in Computer Engineering, Electrical Engineering or Engineering Science
Comments:Staff level calls for 8+ years work experience
Category:IT  code:new
 
 
Job Requirements
 
 
ASIC,Cadence,FPGA,Multimedia,OpenGL,Perl,Python,Wireless
 

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Recruiter
Amitoz Bhalla
 
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