ASIC Design and Implementation Engineer

 
Location: San Diego, California
Posted On: 4/12/2017
Job Code: 1951269_4982
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Job Description
 
Job Overview:
• The responsibilities of this position include: UPF based physical synthesis
• Power content definition using UPF Timing constraints and timing closure Design for test
• Performing ECO using conformal and Verdi Clock domain crossing check by using Spyglass or 0in RTL lint check

Minimum Qualifications:
• Minimum 5 years of experience with implementation of complex subsystem with multiple power domains and has experience of at least two tape-out.

Preferred Qualifications:
• Proficient in following tools and flows, DC, DCT, or DCG UPF Prime time Timing constraints capture in TCL CLP UPF Clock-domain-crossing
• It is also preferred if the candidate has RTL design experience with in-depth knowledge of low power design.
• Familiar with Verilog and system Verilog.

Education:
• Required: Bachelor's, Computer Engineering and/or Electrical Engineering
• Preferred: Master's, Electrical Engineering or equivalent experience
Category:IT  code:new
 
 
Job Requirements
 
 
Engineering,Verilog
 

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Contact Details
 
Recruiter
Satthiseelan Pr
 
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