Verification Engineer

Location: Bayan Lepas, Penang
Posted On: 5/4/2017
Job Code: Verification Enginee
Job Description
• Must have experience performing ASIC - Verification based on architectural/micro-architectural specification review and analysis followed with definition of - Verification requirements.
• Develop tests and test bench components from high Ievel - Verification plans, as well as debug of failing tests, definition of functional coverage space, implementation of coverage monitors and analysis of test coverage space, regression running and debugging failing tests, design and development of test bench collateral.
• Team members will also work closely with design and architecture teams to review and refine test and coverage requirements.
• Required education -BSEE/CE minimum, MS preferred.Also required is 5-10 years, experience in ASIC Iogic - Verification and strong software skills with experience using 1 or more of the following Ianguages: System - Verilog/Verilog, Perl, C/C++.
• Experience with RTL simulators, - VCS preferred, experience specifying and developing test bench components, specifying, developing, and debugging functional tests, and experience specifying, implementing and analyzing functional coverage.
• Strong debug abilities, good interpersonal skills and the ability to work in a highly cooperative team environment across many time zones are also desirable.
• A strong background specifying and developing random test environments is also desired.
Category:IT  code:new
Job Requirements
Verilog /Verilog, Perl, C/C++, RTL simulators

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Contact Details
Dixit Patel
E-mail Address