Network Processor Modeling Engineer

 
Location: San Jose, California
Posted On: 9/13/2017
Job Code: 1958697_NW
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Job Description
 
Job Description:
• This exciting position involves working with complex simulation models for a QC Network Processor.
• The successful candidate will support a CPU emulation model and associated tools used for simulation, design verification and virtualization.
• They will help develop SystemC/TLM Models for QC IPs, and will work with the team to integrate these IP Models to a higher level and verify IP/System Level use cases.
• Verify correct implementation of components, develop integration test plan and test cases.
• Work with Systems, Hardware & Software teams to understand the design requirements, specification and interface details.
• You will be working with technology teams to develop and validate C/C++ based models and SystemC TLM models for multiple peripherals and other IP; analyzing product and hardware/software architecture requirements to design complete SystemC IP models.
• Successful candidates will: Work with Hardware Designers and Verification engineers to implement processor features, new instructions and verification features.
• Model CPU and Hardware operations Develop and debug processor and system use-cases and test cases to validate the design Develop component testbenches and control software (test clients)

Minimum Qualifications:
• 5-10+ years of experience in hardware or software development/test
• Minimum of 5-8 years industry experience in the following areas: Modeling, with an emphasis on Hardware/Software design Computer architecture, CPU microarchitecture knowledge Exposure to or experience with CPU modeling (Instruction Set Simulators) Object Oriented design principles
• Familiars with running and debugging processor Verilog simulations and emulation runs Integrate component models into higher level simulations
• Strong background in C, C++, Python, TCL and CPU architectures

Preferred Qualification:
• Familiar with SystemC modeling, TLM Experience developing unit test and integration tests for component models per specification.
• Design and development of C and/or C++ component models for IP blocks based specifications (NOT RTL SIMULATIONS AND VERILOG SIMULATIONS)
• Familiar with open source machine emulators, like Qemu.
• Familiar with Assembly Language programming
• Experience in Hardware/Software test and validation for SystemC Models at IP/Subsystem/Full chip level platforms.
• Familiar with embedded SW based system model verification methodologies and test automation
• Familiar with Virtual Modeling, e.g. Synopsys Virtio

Education:
• Required: Bachelor's, Computer Engineering and/or Computer Networks & Systems and/or Computer Science and/or Electrical Engineering
• Preferred: Master's, Computer Engineering and/or Computer Networks & Systems and/or Computer Science and/or Electrical Engineering or equivalent experience
Category:IT  code:new
 
 
Job Requirements
 
 
Automation, Architecture, Embedded, Engineering, Tcl, Verilog, Software Development, Python, C++
 

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Contact Details
 
Recruiter
Satthiseelan Pr
 
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