Senior DFT Engineer

 
Location: San Jose, California
Posted On: 9/11/2017
Job Code: 8582
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Job Description
 
• Currently seeking a candidate responsible for the implementation of advanced DFT/DFD (design for test/design for debug) techniques for low power, high performance and highly integrated SoCs.
• The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning.
• In addition, candidate selected will also be involved in all aspects of DFT including architecture, methodology development, design, vector development, manufacturing testing, and debug.

Minimum Qualification:
• 5-10 years of industry experience in the following areas:
• DFT/DFD techniques for complex SoCs
• Fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other models
• JTAG, MBIST, IO Bist, Scan Compression, ATPG, and at-speed testing
• Industry standard ATPG tools like Mentor TestKompress
• Industry standard MBIST tools such as Mentor Tessent MBIST
• Scan insertion using DFT Compiler or equivalent - Logic design, Verilog RTL and verification
• Scripting in Perl and Tcl
• Industry standard simulation tools such as VCS, Questa or NCVerilog
• Verification and validation of DFT features - Silicon bring-up, debug of DFT features on ATE - Verification of the DFT structures
• ATPG Pattern generation, logic simulation, debug on ATE Responsibilities:
• Implementation of advanced DFT/DFD (design for test/design for debug) techniques for high performance, highly integrated SoCs.
• Work with design teams to improve low coverage on designs to desired target. - Architect DFT features, including high-speed IO DFT, MBIST and functional based DFT.
• Work with Test Engineers to debug/diagnose manufacturing defects

Preferred Qualification:
• Experience defining/bring-up of DFT architecture, including hierarchical core/chip based flows
• Experience with large device test on ATE and with architecting DFT strategies in support of multi-core and parallel testing

Education:
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering or equivalent experience
Category:IT  code:new
 
 
Job Requirements
 
 
• 5-10 years of industry experience in the following areas:
• JTAG, MBIST, IO Bist, Scan Compression, ATPG, and at-speed testing
• DFT/DFD techniques for complex SoCs
• Industry standard MBIST tools such as Mentor Tessent MBIST
• Required: Bachelor's, Electrical Engineering
 

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Contact Details
 
Recruiter
Shrey Sharma
 
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E-mail Address
 
LinkedIn
linkedin.com/in/shreysharma1