DFT Engineer

Location: San Diego, California
Posted On: 9/11/2017
Job Code: 1952766_DFT
Job Description
Job Description:
• The Digital ASIC Design For Test (DFT) Team is currently seeking candidates for a senior position aiding in the construction of systems related to storage of Memory BIST failure data.
• The design & implementation of these DFT related digital circuits are intended to reduce test cost, increase production quality and improve the yield learning cycle.
• The position requires writing programs to manipulate RTL and netlists to integrate test structures into the designs.

Minimum Qualifications:
• Experience in Logic Design, System Verilog, Verilog RTL. Ability to understand memory structures and testing methodology.
• Working history of manipulation of Verilog netlists via scripting language; Perl/Python/TCL/language parsers.
• Solid background in ATPG: scan insertion and scan chain stitching; stuck-at & at-speed fault detection; BISR & MISR constructs; clocking methods of test circuitry.
• Experience with JTAG: Tap controllers; TAP interface signaling.
• Proven experience on design verification; assertions; coverage; formal verification.
• Experience with industry simulation tools such as VCS, Modelsim, etc;
• Knowledge and experience of timing closure.
• Knowledge of CTS and related clocking structures and clock control.
• Detail oriented with strong organizational, problem solving and communication skills.

• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering or equivalent experience
Category:IT  code:new
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Contact Details
Satthiseelan Pr