High-Speed Analog & Mixed-Signal Serdes PHY Design

Location: San Diego, California
Posted On: 9/8/2017
Job Code: 1955114_4982
Job Description
Job Description:
• Looking for a mid level analog and mixed-signal circuit designer to work on SerDes PHY designs.
• This designer will be involved in delivering next-generation 10-12Gbps PHY designs for SoCs and will be part of a growing team involved in leading-edge CMOS process technology nodes at 14nm and beyond.
• Design goals also include low-power analog designs to address QC's low-power wireless products.
• The primary responsibility of this position entails working within a team to deliver analog and mixed-signal transistor level circuit designs along with the physical layouts of the high speed circuits for high-speed, low-power PHY SerDes blocks.
• Standard knowledge of PCIe, USB, MPHY is a plus.

Minimum Qualifications:
• Experience in designing op-amps, CML, PLL, DLL, TX driver, CTLE, CDR, DFE
• Experience in using SPICE simulators (Cadence Analog Artist experience is preferred).
• Experience using schematic capture tools (Virtuoso preferred).
• Signal integrity in high speed wireline design
• Full-custom analog layout techniques and the ability to take a design and do all the layout post extract verification and sign-off

Preferred Qualification:
• Understanding of CMOS process effects on designs and layout of Finfet technology

• Required: Bachelor's, Computer Engineering
• Preferred: Master's, Computer Engineering or equivalent experience
Category:IT  code:new
Job Requirements
Senior Staff

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Contact Details
Satthiseelan Pr