Circuit Design Verification Engineer

 
Location: San Diego, California
Posted On: 9/8/2017
Job Code: 1958380_Verification
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Job Description
 
Job Description:
• Applicant will do design/validation of digital and mixed-signal sensor IP in SoC, which includes design verification, spice modeling/simulation, verilog/RTL modeling & simulation, IP integration, scripting for automation.
• The candidate must have a proven record of design verification in advanced CMOS process technologies for volume production.
• Work as part of the IP design team to enable sensor IPs in advanced SOC.
• Handle spice/Verilog simulations of sensor IP. Participate in digital circuit design (RTL).
• Enhance IP characterization/validation by using automation to optimize the flow.
• Support IP release and integration in SOC design.

Minimum Qualifications:
• 3+ years of industrial experience in CMOS digital design (RTL)/validation.
• Hands on experience running Spice/verilog simulation are required.
• Familiar with IP verification flow/tools.
• Proficiency in unix scripting.
• Knowledge of custom layout extraction in Cadence environment Excellent in communication and good team player.
• Education, BSEE or higher.

Education:
• Required: Bachelor's, Electrical Engineering Preferred: Master's
Category:IT  code:new
 
 
Job Requirements
 
 
Cadence, Engineering, Verilog, UNIX, Automation, Digital Design
 

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Contact Details
 
Recruiter
Satthiseelan Pr
 
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