Hardware Engineer

Location: San Jose, California
Posted On: 9/8/2017
Job Code: VE_SC_01
Job Description
Title/Job ID: Sr. Verification Engineer (Logic Verification)
Location: San Jose, CA
Duration: 3 Months (possible Extension)
Job Description: We are looking for individuals to fill positions for Logic Verification Engineers
Candidates must have experience performing ASIC Verification based on architectural/micro-architectural specification review and analysis followed with definition of Verification requirements.
Skill sets required, not limited to the following:
• A strong background in specifying and developing random test bench environments
• Strong background in System Verilog, VMM/UVM and C/C++
• Strong understanding of Hardware Design, Verification and Validation Principles
• Strong experience with Verilog and System Verilog design of complex IP blocks working with high speed design.
Strong background in the following verification disciplines:
• Test bench architecture, test case development, functional coverage, coverage collection and analysis
• Demonstrated ability to create and document verification plans
• Experience with high-speed transceiver protocols PCI E is must and UPI
• Experience with high-speed memory protocols including DDR3/4, QDR and HBM2
• Experience with microcontroller subsystem verification
• Experience with formal verification methods property checking
• Experience verifying design-for-test DFT logic
• Strong verbal and written communication skills
Educational requirements for this position:
• BSEE/CE minimum, MS preferred plus 5-10 years of experience in ASIC Logic Functional Verification
Preferred skills:
• Strong background in design verification, Knowledge of UVM based methodologies preferred
Category:IT  code:new
Job Requirements
System Verilog, VMM/UVM, C/C++, PCI E, DDR3/4, QDR, HBM2

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Contact Details
Abhijit Junnarkar