Digital Verification Engineer

Location: San Jose, California
Posted On: 8/11/2017
Job Code: 1957579
Job Description
-----------------------------Telecom Client looking for suitable candidates urgently--------------------------------------
Minimum Qualification:
Experience with pre-silicon design and verification languages, processes, tools and techniques including SystemVerilog, SystemVerilog Assertions, assertion-based verification, protocol verification, test planning, constrained-random UVM testbench design, simulation, functional coverage closure, scripting in Perl/Python, waveform and interactive debug.

Job Overview:
Develop Verification Infrastructure and tests using SystemVerilog UVM and Formal for wireless protocols including Bluetooth, Zigbee, NFC.
Category:IT  code:new
Job Requirements
Preferred Qualification:
Knowledge of wireless networking protocols; AMBA, AXI, AHB protocols; signal processing;

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Contact Details
Shilpi Shukla
E-mail Address