DFT Engineer

 
Location: San Diego, California
Posted On: 8/4/2017
Job Code: 1957646_DFT
Print
 
Job Description
 
Job Description:
• The Digital ASIC Design Team is currently seeking candidates for a junior position responsible for the implementation of advanced DFT/DFD(design for test/design for debug) techniques for low power, high performance and highly integrated SoCs including CODEC and high-speed PHY & SerDes systems.
• The successful candidate will help in the deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning. Deployment and implementation of advanced DFT/DFD(design for test/design for debug) techniques for low power, high performance and highly integrated SoCs including CODEC and high-speed PHY & SerDes systems.
• Deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning.

Minimum Qualifications:
• Strong fundamental knowledge of DFT/DFD techniques for high performance processors.
• Understanding of core-based test methodology and scan isolation.
• Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models.
• Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.
• Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Mentor Fastscan ATPG tools.
• Synopsys DFTC scan insertion.
• Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis.

Preferred Qualification:
• 2-4 years of industry experience

Education:
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's
Category:IT  code:new
 
 
Job Requirements
 
 
Cadence, Engineering, Verilog, VHDL, ASIC
 

Not Ready to Apply?
Contact Details
 
Recruiter
Satthiseelan Pr
 
Phone
 
 
LinkedIn